Senior Scientist - Fan Out Wafer Level Packaging/Heterogeneous Integration Technologies

Senior Scientist - Fan Out Wafer Level Packaging/Heterogeneous Integration Technologies

SAL - Silicon Austria Labs

Villach, Austria

YOUR FUTURE RESPONSIBILITIES

• Coordination of infrastructure ramp up for FOWLP line at Silicon Austria labs;
• Development and optimization of FOWLP processes for both chip-first and chip-last approaches, including die placement, wafer-level molding, processing of RDL & TMV;
• Designing fan-out package layouts, considering electrical performance, thermal dissipation, and reliability;
• Concept development, DOE planning, and characterization in an interdisciplinary team;
• Development of FOWLP SIP for Power Electronics, MEMS and RF devices;
• Contributing to different industrial projects;
• Data analysis;
• Technical reporting and scientific dissemination;
• Project management.

YOUR PROFILE

• M.Sc. + 7 years of relevant working experience (or higher) in Physics, microsystems fabrication, power electronics and electronics engineering or relevant industrial experience;
• In-depth knowledge and hands-on experience with FOWLP processes, materials, and equipment;
• Familiarity with packaging design tools, such as Cadence or Mentor Graphics for layout and design rule checks;
• Cleanroom and microfabrication experience;
• Project management experience as well as research funding proposals;
• Fluent oral and written communication skills in English, knowledge of German is a plus.

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